Key distinctions

How memory fits around an AI accelerator

Accelerator package

GPU chip

Compute cores + SRAM cache

HBM · DRAM

Working data near the GPU

Server memory · DRAM

For example, DDR5 modules used by the CPU

Storage · NAND / SSD

Keeps files and datasets when powered off

Conceptual layout for an HBM-based accelerator, not a data-flow diagram or a capacity/speed scale. Designs and data paths vary; not every GPU uses HBM. Server DRAM and storage connect through the system, not necessarily directly to each other. Architecture example: NVIDIA Hopper ↗

Compare the trade-offs

Bandwidth is data moved per second; latency is the wait for an access; capacity is how much fits. A high-bandwidth product is not automatically the lowest-latency option.

SRAM, DRAM, HBM and NAND at a glance
TechnologyRoleStrengthTrade-off
SRAMFast working memory often used in small caches close to a processor.Low access latency; no periodic refresh.Larger cells mean less capacity per area and higher cost per bit.
DRAMWorking memory that temporarily holds data while a computer runs.More capacity per chip area than SRAM.Needs refresh; slower access than SRAM.
HBMA DRAM subtypeStacked DRAM built to move large amounts of data to an accelerator.High bandwidth in a compact package near the accelerator.Stacking, packaging and cooling add engineering complexity.
NANDStorage chips that keep data when power is off.Retains data without power; suited to large storage capacity.Slower than working memory; write endurance is finite.

SRAM needs no periodic refresh, but it still loses data without power. DRAM—including HBM—also needs power and refresh. Only NAND in this comparison is non-volatile.

Who supplies what?

Selected US-listed examples, not a complete supplier list or a ranking. A technology’s use in AI does not establish how much of a company’s revenue comes from AI.

SRAM

GSI Technology (GSIT): sells standalone SRAM and also develops APU products. Standalone SRAM is not the embedded cache inside every AI chip.

Supplier product source ↗

NVIDIA designs accelerators that incorporate caches and use external memory. That does not make NVIDIA a merchant supplier of standalone SRAM; nor does more GPU cache automatically create orders for GSI Technology.

Micron business & financials →Sandisk business & financials →

Investment research framework

These are editorial research prompts, not return forecasts. Read the latest dated company disclosures before drawing a company-level conclusion.

  1. HBM expansion announced? Check customer qualification, usable output and shipment timing. Then compare margins and capital spending; announced capacity is not recognized revenue.
  2. DRAM or NAND prices rising? Separate price increases from shipment growth. Compare inventories and new supply, and avoid treating one strong quarter as permanent earnings.
  3. An AI chip uses more SRAM? Identify whether it is embedded cache or a separately purchased component. Confirm a supplier relationship before assuming a listed company benefits.
  4. Business growth and valuation Compare cash generation, debt, dilution and the valuation already paid. Better technology alone does not establish an attractive stock price.
Place memory in the AI supply-chain map →

Technical sources

Back to all AI terms →